1. Technical Field
Various embodiments relate to a semiconductor integrated circuit, and more particularly, to a semiconductor memory apparatus.
2. Related Art
In general, a semiconductor memory apparatus as a volatile memory device includes a memory cell which is constituted by a capacitor. Since the semiconductor memory apparatus includes the memory cell constituted by the capacitor, loss of charges charged in the capacitor is caused, and due to this fact, the semiconductor memory apparatus is called a volatile memory device.
Referring to FIG. 1, a conventional semiconductor memory apparatus includes a memory cell 10, a first equalizer unit 20, a bit line disconnection unit 30, a second equalizer unit 40, a sense amplifier 50, and a data transfer unit 60.
The memory cell 10 is coupled to a bit line BL when a word line WL is enabled. The memory cell 10 includes a first transistor N1 and a capacitor C1. The first transistor N1 has a gate to which the word line WL is coupled and a drain and a source to which the bit line BL and one end of the capacitor C1 are coupled. The capacitor C1 has one end to which the first transistor N1 is coupled and the other end which is applied with a cell plate voltage VCP.
The first equalizer unit 20 couples the bit line BL and a bit line bar BLb with each other when a bit line equalizer signal BLEQ is enabled.
The first equalizer unit 20 includes a second transistor N2. The second transistor N2 has a gate which is inputted with the bit line equalizer signal BLEQ and a drain and a source to which the bit line BL and the bit line bar BLb are coupled.
The bit line disconnection unit 30 decouples the bit line BL and the bit line bar BLb from the sense amplifier 50 when a bit line isolation signal BIS is enabled. Also, the bit line disconnection unit 30 couples the bit line BL and the bit line bar BLb with the sense amplifier 50 when the bit line isolation signal BIS is disabled.
The bit line disconnection unit 30 includes third and fourth transistors N3 and N4. The third transistor N3 has a gate which is inputted with the bit line isolation signal BIS and a drain and a source to which the bit line BL and the sense amplifier 50 are coupled. The fourth transistor N4 has a gate which is inputted with the bit line isolation signal BIS, and a drain and a source to which the bit line bar BLb and the sense amplifier 50 are coupled.
The second equalizer unit 40 couples a node to which the bit line BL and the sense amplifier 50 are coupled and a node to which the bit line bar BLb and the sense amplifier 50 are coupled, when the bit line equalizer signal BLEQ is enabled, and applies a bit line precharge voltage VBLP to both nodes.
The second equalizer unit 40 includes fifth and sixth transistors N5 and N6. The fifth transistor N5 has a gate which is inputted with the bit line equalizer signal BLEQ and a drain and a source to which the node coupled to the bit line BL and the sense amplifier 50 and the sixth transistor N6 are coupled. The sixth transistor N6 has a gate which is inputted with the bit line equalizer signal BLEQ and a drain and a source to which the node coupled to the bit line bar BLb and the sense amplifier 50 and the fifth transistor N5 are coupled. The bit line precharge voltage VBLP is applied to a node to which the fifth and sixth transistors N5 and N6 are coupled.
The sense amplifier 50 senses and amplifies the voltage difference between the bit line BL and the bit line bar BLb.
The sense amplifier 50 includes seventh to tenth transistors P1, P2, N7 and N8. The seventh transistor P1 has a source which is applied with a first driving voltage RTO and a gate to which the bit line bar BLb is coupled. The eighth transistor P2 has a source which is applied with the first driving voltage RTO and a gate to which the bit line BL is coupled. The ninth transistor N7 has a gate to which the bit line bar BLb is coupled, a drain to which the drain of the seventh transistor P1 is coupled, and a source which is applied with a second driving voltage SB. The tenth transistor N8 has a gate to which the bit line BL is coupled, a drain to which the drain of the eight transistor P2 is coupled, and a source which is applied with the second driving voltage SB. The bit line BL is coupled to a node to which the seventh and the ninth transistors P1 and N7 are coupled, and the bit line bar BLb is coupled to a node to which the eighth and tenth transistors P2 and N8 are coupled. The first and second driving voltages RTO and SB as voltages for activating the sense amplifier 50 are voltages which are applied to the sense amplifier 50 when a sense amplifier enable signal (SAE) is enabled. For, example, a sense amplifier driving unit (70) generates the first and second driving voltages RTO and SB when the sense amplifier enable signal (SAE) is enabled.
The data transfer unit 60 transfers the voltage amplified in the sense amplifier 50, to a data line DATA_L and a data line bar DATA_Lb when a column select signal YI is enabled.
The data transfer unit 60 includes eleventh and twelfth transistors N9 and N10. The eleventh transistor N9 has a gate which is inputted with the column select signal YI and a drain and a source to which a node coupled with the bit line BL and the sense amplifier 50 and the data line DATA_L are coupled. The twelfth transistor N10 has a gate which is inputted with the column select signal YI and a drain and a source to which a node coupled with the bit line bar BLb and the sense amplifier 50 and the data line bar DATA_Lb are coupled.
The conventional semiconductor memory apparatus configured as described above operates as follows.
As the word line WL is enabled, the memory cell 10 and the bit line BL are coupled. As the charges of the capacitor C1 of the memory cell 10 are transferred to the bit line BL, a voltage difference occurs between the bit line BL and the bit line bar BLb.
The bit line disconnection unit 30 couples the bit line BL and the bit line bar BLb to the sense amplifier 50 when the bit line isolation signal BIS is disabled.
The sense amplifier 50 senses and amplifies the voltage difference between the bit line BL and the bit line bar BLb.
The data transfer unit 60 transfers the voltage amplified by the sense amplifier 50, to the data line DATA_L and the data line bar DATA_Lb when the column select signal YI is enabled.
In this way, the semiconductor memory apparatus which stores data using the capacitor C1 is configured to sense and amplify the voltage difference between the bit line BL and the bit line bar BLb, resulting from the charge amount of the capacitor C1, and output the amplified voltage to an outside of the semiconductor memory apparatus.
The semiconductor memory apparatus including the memory cell constituted by the capacitor is utilized as a volatile memory in a number of industrial fields as described above.
Research has continuously been made to allow a semiconductor memory apparatus including a memory cell constituted by a resistive device to replace the semiconductor memory apparatus including the memory cell constituted by the capacitor and to be used in an industrial field.